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CY7C109D CY7C1009D
1-Mbit (128K x 8) Static RAM
Features
* Pin- and function-compatible with CY7C109B/CY7C1009B * High speed -- tAA = 10 ns * Low active power -- ICC = 80 mA @ 10 ns * Low CMOS standby power -- ISB2 = 3 mA * 2.0V Data Retention * Automatic power-down when deselected * TTL-compatible inputs and outputs * Easy memory expansion with CE1, CE2 and OE options * CY7C109D available in Pb-free 32-pin 400-Mil wide Molded SOJ and 32-pin TSOP I packages. CY7C1009D available in Pb-free 32-pin 300-Mil wide Molded SOJ package
Functional Description [1]
The CY7C109D/CY7C1009D is a high-performance CMOS static RAM organized as 131,072 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE1), an active HIGH Chip Enable (CE2), an active LOW Output Enable (OE), and tri-state drivers.The eight input and output pins (IO0 through IO7) are placed in a high-impedance state when: * Deselected (CE1 HIGH or CE2 LOW), * Outputs are disabled (OE HIGH), * When the write operation is active (CE1 LOW, CE2 HIGH, and WE LOW) Write to the device by taking Chip Enable One (CE1) and Write Enable (WE) inputs LOW and Chip Enable Two (CE2) input HIGH. Data on the eight IO pins (IO0 through IO7) is then written into the location specified on the address pins (A0 through A16). Read from the device by taking Chip Enable One (CE1) and Output Enable (OE) LOW while forcing Write Enable (WE) and Chip Enable Two (CE2) HIGH. Under these conditions, the contents of the memory location specified by the address pins appears on the IO pins.
Logic Block Diagram
INPUT BUFFER A0 A1 A2 A3 A4 A5 A6 A7 A8
IO0 IO1
ROW DECODER
128K x 8 ARRAY
SENSE AMPS
IO2 IO3 IO4 IO5 IO6
CE1 CE2 WE OE
COLUMN DECODER
POWER DOWN
IO7
Note 1. For guidelines on SRAM system design, please refer to the `System Design Guidelines' Cypress application note, available on the internet at www.cypress.com.
Cypress Semiconductor Corporation Document #: 38-05468 Rev. *E
*
A9 A10 A11 A12 A13 A14 A15 A16
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised February 22, 2007
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CY7C109D CY7C1009D
Pin Configurations [2]
SOJ Top View
A11 A9 A8 A13 WE CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CE IO7 IO6 IO5 IO4 IO3 GND IO2 IO1 IO0 A0 A1 A2 A3
NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 IO 0 IO 1 IO 2 GND
TSOP I Top View (not to scale)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
VCC A15 CE2 WE A13 A8 A9 A11 OE A10 CE1 IO 7 IO 6 IO 5 IO 4 IO 3
Selection Guide
CY7C109D-10 CY7C1009D-10 Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current 10 80 3 Unit ns mA mA
Note 2. NC pins are not connected on the die.
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CY7C109D CY7C1009D
Maximum Ratings
Exceeding the maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage on VCC to Relative GND [3] ... -0.5V to +6.0V DC Voltage Applied to Outputs in High-Z State [3] ...................................-0.5V to VCC + 0.5V DC Input Voltage [3] ............................... -0.5V to VCC + 0.5V Current into Outputs (LOW) ........................................ 20 mA Static Discharge Voltage........................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current .................................................... > 200 mA
Operating Range
Range Industrial Ambient Temperature -40C to +85C VCC 5V 0.5V Speed 10 ns
Electrical Characteristics (Over the Operating Range)
Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage
[3]
Test Conditions IOH = -4.0 mA IOL = 8.0 mA
7C109D-10 7C1009D-10 Min 2.4 0.4 2.2 -0.5 VCC + 0.5 0.8 +1 +1 80 72 58 37 10 Max
Unit V V V V A A mA mA mA mA mA
Input Leakage Current Output Leakage Current
GND < VI < VCC GND < VI < VCC, Output Disabled 100 MHz 83 MHz 66 MHz 40 MHz
-1 -1
VCC Operating Supply Current VCC = Max, IOUT = 0 mA, f = fmax = 1/tRC
ISB1
Automatic CE Power-Down Current--TTL Inputs Automatic CE Power-Down Current--CMOS Inputs
Max VCC, CE1 > VIH or CE2 < VIL, VIN > VIH or VIN < VIL, f = fmax Max VCC, CE1 > VCC - 0.3V, or CE2 < 0.3V, VIN > VCC - 0.3V, or VIN < 0.3V, f = 0
ISB2
3
mA
Note 3. VIL (min) = -2.0V and VIH(max) = VCC + 1V for pulse durations of less than 5 ns.
Document #: 38-05468 Rev. *E
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CY7C109D CY7C1009D
Capacitance [4]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 5.0V Max 8 8 Unit pF pF
Thermal Resistance [4]
Parameter JA JC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Still Air, soldered on a 3 x 4.5 inch, four-layer printed circuit board 300-Mil Wide SOJ 57.61 40.53 400-Mil Wide SOJ 56.29 38.14 TSOP I 50.72 16.21 Unit C/W C/W
AC Test Loads and Waveforms [5]
ALL INPUT PULSES 90% 10% 90% 10%
Z = 50 OUTPUT 50 * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT 1.5V
3.0V
30 pF*
GND
Rise Time: 3 ns
(a)
(b)
Fall Time: 3 ns
High-Z characteristics: 5V OUTPUT INCLUDING JIG AND SCOPE 5 pF R2 255 R1 480
(c)
Notes 4. Tested initially and after any design or process changes that may affect these parameters. 5. AC characteristics (except High-Z) are tested using the load conditions shown in Figure (a). High-Z characteristics are tested for all speeds using the test load shown in Figure (c).
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CY7C109D CY7C1009D
Switching Characteristics (Over the Operating Range) [6]
Parameter Read Cycle tpower [7] tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD
[10] [10]
Description
7C109D-10 7C1009D-10 Min Max
Unit
VCC(typical) to the first access Read Cycle Time Address to Data Valid Data Hold from Address Change CE1 LOW to Data Valid, CE2 HIGH to Data Valid OE LOW to Data Valid OE LOW to Low Z OE HIGH to High Z
[8, 9] [9] [8, 9]
100 10 10 3 10 5 0 5 3 5 0 10 10 7 7 0 0 7 6 0 3 5
s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
CE1 LOW to Low Z, CE2 HIGH to Low Z
CE1 HIGH to High Z, CE2 LOW to High Z
CE1 LOW to Power-Up, CE2 HIGH to Power-Up CE1 HIGH to Power-Down, CE2 LOW to Power-Down
[11, 12]
Write Cycle tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE
Write Cycle Time CE1 LOW to Write End, CE2 HIGH to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE HIGH to Low Z
[9]
WE LOW to High Z [8, 9]
Notes 6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 7. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed 8. tHZOE, tHZCE and tHZWE are specified with a load capacitance of 5 pF as in part (c) of "AC Test Loads and Waveforms [5]" on page 4. Transition is measured when the outputs enter a high impedance state. 9. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 10. This parameter is guaranteed by design and is not tested. 11. The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 HIGH, and WE LOW. CE1 and WE must be LOW and CE2 HIGH to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 12. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
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CY7C109D CY7C1009D
Data Retention Characteristics (Over the Operating Range)
Parameter VDR ICCDR tCDR [4] tR
[13]
Description VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time
Conditions VCC = VDR = 2.0V, CE1 > VCC - 0.3V or CE2 < 0.3V, VIN > VCC - 0.3V or VIN < 0.3V
Min 2.0
Max 3
Unit V mA ns ns
0 tRC
Data Retention Waveform
DATA RETENTION MODE
VCC
4.5V tCDR
VDR > 2V
4.5V tR
CE
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled) [14, 15]
tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID
Read Cycle No. 2 (OE Controlled) [15, 16]
ADDRESS tRC CE1 CE2 OE tDOE DATA OUT VCC SUPPLY CURRENT tLZOE HIGH IMPEDANCE tLZCE tPU 50% DATA VALID tPD 50%
tACE tHZOE tHZCE HIGH IMPEDANCE
ICC ISB
Notes 13. Full device operation requires linear VCC ramp from VDR to VCC(min) > 50 s or stable at VCC(min) > 50 s. 14. Device is continuously selected. OE, CE1 = VIL, CE2 = VIH. 15. WE is HIGH for read cycle. 16. Address valid prior to or coincident with CE1 transition LOW and CE2 transition HIGH.
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CY7C109D CY7C1009D
Switching Waveforms (continued)
Write Cycle No. 1 (CE1 or CE2 Controlled) [17, 18]
tWC ADDRESS CE1 tSA CE2 tAW tPWE WE tSD DATA IO DATA VALID tHD tSCE tHA tSCE
Write Cycle No. 2 (WE Controlled, OE HIGH During Write) [17, 18]
tWC ADDRESS tSCE CE1 CE2 tAW tSA WE tPWE
tSCE tHA
OE tSD DATA IO NOTE 19 tHZOE DATAIN VALID t HD
Notes 17. Data IO is high impedance if OE = VIH. 18. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE going HIGH, the output remains in a high-impedance state. 19. During this period the IOs are in the output state and input signals should not be applied.
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CY7C109D CY7C1009D
Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, OE LOW) [12, 18]
tWC ADDRESS tSCE CE1 CE2 tSCE tAW tSA WE tSD DATA IO NOTE 19 tHZWE DATA VALID tLZWE tHD tPWE tHA
Truth Table
CE1 H X L L L CE2 X L H H H OE X X L X H WE X X H L H High Z High Z Data Out Data In High Z IO0-IO7 Power-down Power-down Read Write Selected, Outputs Disabled Mode Power Standby (ISB) Standby (ISB) Active (ICC) Active (ICC) Active (ICC)
Ordering Information
Speed (ns) 10 Ordering Code CY7C109D-10VXI CY7C109D-10ZXI CY7C1009D-10VXI Package Diagram 51-85033 51-85056 51-85041 Package Type 32-pin (400-Mil) Molded SOJ (Pb-free) 32-pin TSOP Type I (Pb-free) 32-pin (300-Mil) Molded SOJ (Pb-free) Operating Range Industrial
Please contact your local Cypress sales representative for availability of these parts.
Document #: 38-05468 Rev. *E
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CY7C109D CY7C1009D
Package Diagrams
Figure 1. 32-pin (300-Mil) Molded SOJ, 51-85041
51-85041-*A
Figure 2. 32-pin (400-Mil) Molded SOJ, 51-85033
51-85033-*B
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CY7C109D CY7C1009D
Package Diagrams (continued)
Figure 3. 32-pin Thin Small Outline Package Type I (8x20 mm), 51-85056
51-85056-*D
All product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05468 Rev. *E
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(c) Cypress Semiconductor Corporation, 2006-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY7C109D CY7C1009D
Document History Page
Document Title: CY7C109D/CY7C1009D, 1-Mbit (128K x 8) Static RAM Document Number: 38-05468 REV. ** *A *B ECN NO. 201560 233722 262950 Issue Date See ECN See ECN See ECN Orig. of Change SWI RKF RKF Description of Change Advance Information data sheet for C9 IPP DC parameters are modified as per EROS (Spec # 01-2165) Pb-free offering in Ordering Information Added Data Retention Characteristics table Added Tpower Spec in Switching Characteristics Table Shaded Ordering Information Reduced Speed bins to -10 and -12 ns Converted from Preliminary to Final Removed Commercial Operating range Removed 12 ns speed bin Added ICC values for the frequencies 83MHz, 66MHz and 40MHz Updated Thermal Resistance table Updated Ordering Information Table Changed Overshoot spec from VCC+2V to VCC+1V in footnote #3 Changed ICC spec from 60 mA to 80 mA for 100MHz, 55 mA to 72 mA for 83MHz, 45 mA to 58 mA for 66MHz, 30 mA to 37 mA for 40MHz
*C *D
See ECN 560995
See ECN See ECN
RKF VKN
*E
802877
See ECN
VKN
Document #: 38-05468 Rev. *E
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